This invention is applicable to data processing systems with multi-level memory where the second level (L1) memory used for both unified (code and instructions) level two cache and flat (L2 SRAM) memory used to hold critical data and instructions. The second level memory (L2) is used for multiple purposes including unified instruction and data level two cache, directly addressable SRAM memory used to hold critical data and code accessible by both external and internal direct memory access (DMA) units.
When the level one data cache controller is granted access to the level one data cache, this access could force an existing line to be evicted. The CPU can also force the level one data cache to evict lines though the block writeback operation. At the same time, the level two cache could be receiving a DMA access to the same line. This situation could break coherency, if DMA data were committed incorrectly. This could occur by writing to the level two memory then overwriting that data with the level one cache victim. This could also occur by sending the DMA data as a snoop write to the level one data cache. This forces the level one data cache to write the DMA data to its cache after the victim has been evicted. This effectively, drops the DMA write. Thus when a victim is in progress, a DMA write sent as snoop could miss the victim.
Creating a heterogeneous multi-processor system can have many advantages and added flexibility. This comes with many challenges. The multiple processing cores possibly have different bus protocols. This creates a problem in how to you integrate components efficiently which speak different languages. These different protocols often make different ordering guarantees that must be unified without demolishing performance of either. The multiple processing cores may have different operating frequencies that aren't necessarily integral multiples of each other. This creates a problem in how to integrate these together to get maximum utilization of both, how to get these heterogeneous processors to work well together. There is a problem in how each processor operate individually at full utilization and efficiently share data. Answering these questions has a major effect on the overall efficiency and performance of the system.